1. Field of the Invention
The present invention relates to a semiconductor integrated circuit.
2. Description of Related Art
Semiconductor integrated circuits (LSIs) called “semi-custom ICs” such as gate arrays and cell-based ICs (standard cells) have become popular. In the case of the cell-based IC, a desired circuit is achieved by placing basic logic cells such as a two-input NAND, an inverter and a flip-flop on a well (substrate). In the cell-based IC, regions where basic logic cells are placed and regions where no basic logic cell is placed are mixed.
A process for fabricating a semiconductor integrated circuit includes CMP (Chemical Mechanical Polishing). In the CMP, a wafer surface is physically and chemically polished to planarize the wafer surface. However, if regions having different local pattern densities exist on the wafer surface as in the cell-based IC, the wafer surface may not become planar and thus a film thickness of the polished film may not become uniform even after the polishing.
A technique of placing a “dummy cell” is known, the purpose of which is to fill a gap where no basic logic cell is placed and thereby to make local densities of diffusion layers and polysilicon equal.
In general, the cell-based IC is designed by the use of a cell library in which data of the basic logic cells and the dummy cells are stored. In a layout design stage of the cell-based IC, the basic logic cells are placed by using delay data, in-cell layout data and the like stored in the cell library, such that a desired circuit performance is achieved. After the basic logic cells are placed, dummy cells are placed at gaps where no basic logic cell is placed.
The semiconductor integrated circuit such as the cell-based IC includes a large number of logic circuits, and each logic circuit is generally provided with at least one transistor. With increasing miniaturization of the semiconductor integrated circuit, characteristics of the transistor included in the logic circuit are more likely to change depending on a peripheral layout pattern surrounding the logic circuit.
For example, the dummy cell in the cell-based IC often has not only the well but also dummy patterns of diffusion layers and polysilicon for equalizing the local pattern density. Electrical characteristics of a basic logic cell vary depending on a peripheral layout pattern surrounding the basic logic cell and thus may deviate from design values stored in the cell library.
As described above, in the case where layout patterns are greatly different by location within a semiconductor integrated circuit (e.g. when basic logic cells are randomly placed), the characteristics of transistor can vary due to the difference in the layout pattern. In order to suppress the variation of the transistor characteristics, for example, some constraints may be imposed on a placement rule of the basic logic cell, or the variation of the transistor characteristics caused by the peripheral layout pattern may be incorporated as a margin at a time when the library of the basic logic cells is created. However, the above-mentioned techniques for suppressing the variation of the transistor characteristics may cause increase in an area and performance degradation of the semiconductor integrated circuit.
Moreover, in recent years, a ratio of variation in an interconnection width due to the OPE (Optical Proximity Effect) to the original interconnection width is getting larger, which affects the transistor characteristics. Therefore, the OPC (Optical Proximity Correction) is performed with respect to a gate polysilicon of a transistor. In the OPC, the variation due to the OPE is estimated based on a distance between adjacent interconnections and a layout data of an interconnection is corrected such that the interconnection width including the variation due to the OPE becomes equal to its design value. In the case where the dummy cell has not only the well but also the dummy patterns of diffusion layers and polysilicon for equalizing the local pattern density, the peripheral pattern surrounding the basic logic cell becomes complicated. As the peripheral pattern becomes more complicated, the OPC procedure becomes more difficult, which causes increase in TAT (Turn Around Time).
It is important in the semiconductor integrated circuit having the dummy cells to suppress the variation in the electrical characteristics of the basic logic cells that is dependent on the peripheral layout pattern. For example, please refer to Japanese Laid-Open Patent Application JP-2004-288685 (hereinafter referred to as Patent Document 1) and Japanese Laid-Open Patent Application JP-2005-340461 (hereinafter referred to as Patent Document 2).
FIG. 1 is a plan view showing a configuration of a dummy cell 101 in a semiconductor integrated circuit described in the Patent Document 1. As shown in FIG. 1, the dummy cell 101 includes a N well 108, a P well 109, a dummy gate polysilicon 115, a contact 106 and a metal power-supply interconnection 107.
FIG. 2 is a plan view showing a configuration of a semiconductor integrated circuit provided with the dummy cells 101. The semiconductor integrated circuit includes a plurality of basic logic cells 102 that are randomly placed. As shown in FIG. 2, the basic logic cell 102 includes a N+ diffusion layer 103, a P+ diffusion layer 104, a gate polysilicon 105, a contact 106 and a metal power-supply interconnection 107. The dummy cell 101 is so placed as to fill a gap between the basic logic cells 102.
According to the dummy cell technique disclosed in the Patent Document 1, the dummy cell 101 has the dummy gate polysilicon 115 that does not form a transistor. The dummy cells 101 are placed on both sides of the basic logic cell 102, and thereby an inter-gate distance 121 between the gate polysilicon 105 of the basic logic cell 102 and the adjacent dummy gate polysilicon 115 is kept constant. Since the inter-gate distance 121 is kept uniform, a time required for the OPC procedure can be reduced and processing accuracy of the gate polysilicon can be improved.
The Patent Document 2 discloses a technique for suppressing variation in characteristics due to manufacturing variability. According to the technique described in the Patent Document 2, basic cells each consisting of a NMOS transistor and a PMOS transistor are placed in a gate array form in order to suppress variation in characteristics of the basic logic cell (buffer). The gate array is constituted by the basic logic cells and the dummy cells. According to the technique described in the Patent Document 2, the dummy cells are placed in a gate array form around a basic logic cell and thus the gate polysilicon and the diffusion layer around the basic logic cell are placed in a regular manner. Since an inter-polysilicon distance between adjacent gate polysilicons is kept constant, the above-mentioned problems are improved in the basic logic cell (buffer).
The inventor of the present application has recognized the following points. In the case where the dummy cells 101 having the dummy gate polysilicon 115 are placed as shown in FIG. 2, the inter-gate distance 121 between the outermost gate polysilicon 105 of the basic logic cell 102 and the adjacent dummy gate polysilicon 115 can be made constant. However, it is difficult to make a distance (inter-diffusion-layer distance 120) between adjacent diffusion layers of the different basic logic cells 102 constant.
Moreover, the typical semiconductor integrated circuit is provided with an STI (Shallow Trench Isolation) structure in order to electrically isolate transistor elements from each other, namely, to electrically isolate diffusion layers of different transistors from each other. In the case where the STI structure is used, there is difference in Si shrinkage factor between SiO2 of the STI structure and the silicon substrate. Consequently, the Si substrate is subjected to compressive stress (STI stress), which can cause variation in a current characteristic of the transistor. The STI stress varies depending on a size of the STI region namely the distance between adjacent diffusion layers. Therefore, when the inter-diffusion-layer distance 120 varies as shown in FIG. 2, the characteristics of the basic logic cell 102 can vary and deviate from the design values stored in the cell library.
Furthermore, according to the technique described in the Patent Document 2, the dummy cells need to be placed in a gate array form to surround the basic logic cell. This may be applicable when the buffer is placed in a region with low layout density. However, it is difficult to apply to a region where a large number of basic logic cells are placed. Even if it is applied, an area becomes extremely large due to the gate array form. Moreover, the dummy cell does not form a logic but forms a transistor. Therefore, the gate or the diffusion layer may be short-circuited with another region due to malfunction of the dummy cell transistor, fine grains such as dust, and the like, which causes a problem.